Physical design to improve the noise immunity of digital circuits in a mixed-signal smart-power system

Existing research in substrate coupling noise in mixedsignal circuits has concen tratedon the problem of the high speed digital circuitry in uencing the highly sensitive analog circuitry [1{6]. It has been demonstrated in the literature that physical design plays an important role in minimizing the in uence of substrate noise generated by the digital circuitry, a ecting the highly sensitive analog circuitry [1{6]. A number of articles [1{5] have reported experimentally observed noise waveforms caused by the high speed switc hing of the on-chip digital CMOS circuits in mixedsignal systems. A typical noise w aveform,bothexperimentally observed and simulated, is shown in Fig. 1. Note that the noise spikes are generated during the digital signal transitions when the circuit dissipates transient power and a current path exists from VDD to GND. No substrate noise is generated while the digital signal is high or low.